Welcome to Journal of Network Communications and Emerging Technologies (JNCET)

Volume 11, Issue 8, August (2021)                               Cover Page and Table of Contents

S.No	Title & Authors	Full Text
1	Zynq FPGA Implementation of LDPC Based on Bit Flipping Algorithm Arwa H. Ashou, Dhafir A. Alneema Abstract - A channel or medium, such as wired or wireless, is used to transmit data from a source to a receiver. The channel medium, as well as external noise, affect the reliability of received data, causing signal interference and introducing errors in transmitted data. LDPC codes are one of the error correction codes with the quickest and most efficient level of information security and correction during contact. As a result of its robust success in correcting errors and ability to satisfy all of the specifications of the 5G communications, this code has been almost universally adopted in networking standards such as satellites and communications networks for error correction. The hardware implementation, however, is a challenge for researchers due to its high complexity and long run time. LDPC codes are one of the most codes for FPGA implementation. This work introduces a hardware LDPC of Bit Flipping algorithm decoder using HLS "High-Level Synthesis" techniques. Given that flexibility is one of the key advantages of FPGAs, HLS is commonly used as a good tool to synthesize hardware. In this work, an optimization techniques including array partitioning and loop unrolling to speed up the execution time and to minimize latency are utilized. The implementation of the BF architecture on Zynq-7000, ZC702 Evaluation Board Part xc7z020clg484-1 is presented in this work and for simulation results, Xilinx Vivado HLS 18.3 is used.	Download